/*******************************************************************************
    Copyright (c) 2013 NVidia Corporation

    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to
    deal in the Software without restriction, including without limitation the
    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
    sell copies of the Software, and to permit persons to whom the Software is
    furnished to do so, subject to the following conditions:

        The above copyright notice and this permission notice shall be
        included in all copies or substantial portions of the Software.

    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
    DEALINGS IN THE SOFTWARE.
*******************************************************************************/

#ifndef _UVM_IOCTL_H
#define _UVM_IOCTL_H

#include "uvmtypes.h"
#include "uvm-debug.h"
#include "uvm_events.h"

#ifdef __cplusplus
extern "C" {
#endif

//
// Please see the header file (uvm.h) for detailed documentation on each of the
// associated API calls.
//

#if defined(WIN32) || defined(WIN64)
#   define UVM_IOCTL_BASE(i)       CTL_CODE(FILE_DEVICE_UNKNOWN, 0x800+i, METHOD_BUFFERED, FILE_READ_DATA | FILE_WRITE_DATA)
#else
#   define UVM_IOCTL_BASE(i) i
#endif

//
// UvmReserveVA
//
#define UVM_RESERVE_VA                                                UVM_IOCTL_BASE(1)

typedef struct
{
    unsigned long long  requestedBase; // IN
    unsigned long long  length;        // IN
    NV_STATUS          rmStatus;     // OUT
} UVM_RESERVE_VA_PARAMS;

//
// UvmReleaseVA
//
#define UVM_RELEASE_VA                                                UVM_IOCTL_BASE(2)

typedef struct
{
    unsigned long long  requestedBase; // IN
    unsigned long long  length;        // IN
    NV_STATUS          rmStatus;     // OUT
} UVM_RELEASE_VA_PARAMS;

//
// UvmRegionCommit
//
#define UVM_REGION_COMMIT                                             UVM_IOCTL_BASE(3)

typedef struct
{
    unsigned long long  requestedBase; // IN
    unsigned long long  length;        // IN
    UvmStream           streamId;      // IN
    UvmGpuUuid          gpuUuid;       // IN
    NV_STATUS          rmStatus;     // OUT
} UVM_REGION_COMMIT_PARAMS;

//
// UvmRegionDecommit
//
#define UVM_REGION_DECOMMIT                                           UVM_IOCTL_BASE(4)

typedef struct
{
    unsigned long long  requestedBase; // IN
    unsigned long long  length;        // IN
    NV_STATUS          rmStatus;     // OUT
} UVM_REGION_DECOMMIT_PARAMS;

//
// UvmRegionSetStream
//
#define UVM_REGION_SET_STREAM                                         UVM_IOCTL_BASE(5)

typedef struct
{
    unsigned long long  requestedBase; // IN
    unsigned long long  length;        // IN
    UvmStream           newStreamId;   // IN
    UvmGpuUuid          gpuUuid;       // IN
    NV_STATUS          rmStatus;     // OUT
} UVM_REGION_SET_STREAM_PARAMS;

//
// UvmSetStreamRunning
//
#define UVM_SET_STREAM_RUNNING                                        UVM_IOCTL_BASE(6)

typedef struct
{
    UvmStream          streamId;  // IN
    NV_STATUS         rmStatus; // OUT
} UVM_SET_STREAM_RUNNING_PARAMS;


//
// Due to limitations in how much we want to send per ioctl call, the nStreams
// member must be less than or equal to about 250. That's an upper limit.
//
// However, from a typical user-space driver's point of view (for example, the
// CUDA driver), a vast majority of the time, we expect there to be only one
// stream passed in. The second most common case is something like atmost 32
// streams being passed in. The cases where there are more than 32 streams are
// the most rare. So we might want to optimize the ioctls accordingly so that we
// don't always copy a 250 * sizeof(streamID) sized array when there's only one
// or a few streams.
//
// For that reason, UVM_MAX_STREAMS_PER_IOCTL_CALL is set to 32.
//
// If the higher-level (uvm.h) call requires more streams to be stopped than
// this value, then multiple ioctl calls should be made.
//
#define UVM_MAX_STREAMS_PER_IOCTL_CALL 32

//
// UvmSetStreamStopped
//
#define UVM_SET_STREAM_STOPPED                                        UVM_IOCTL_BASE(7)

typedef struct
{
    UvmStream          streamIdArray[UVM_MAX_STREAMS_PER_IOCTL_CALL];  // IN
    unsigned long long nStreams;                                       // IN
    NV_STATUS          rmStatus;                                       // OUT
} UVM_SET_STREAM_STOPPED_PARAMS;

//
// UvmMigrateToGpu
//
#define UVM_MIGRATE_TO_GPU                                            UVM_IOCTL_BASE(8)

typedef struct
{
    unsigned long long  requestedBase; // IN
    unsigned long long  length;        // IN
    UvmGpuUuid          gpuUuid;       // IN
    unsigned            flags;         // IN
    NV_STATUS          rmStatus;     // OUT
} UVM_MIGRATE_TO_GPU_PARAMS;

//
// UvmCallTestFunction
//
#define UVM_RUN_TEST                                                  UVM_IOCTL_BASE(9)

typedef struct
{
    UvmGpuUuid         gpuUuid;    // IN
    unsigned           test;       // IN
    NV_STATUS         rmStatus;    // OUT
} UVM_RUN_TEST_PARAMS;

//
// This is a magic offset for mmap. Any mapping of an offset above this
// threshold will be treated as a counters mapping, not as an allocation
// mapping. Since allocation offsets must be identical to the virtual address
// of the mapping, this threshold has to be an offset that cannot be
// a valid virtual address.
//
#if defined(__linux__)
    #if defined(NV_64_BITS)
        #define UVM_EVENTS_OFFSET_BASE   (1UL << 63)
        #define UVM_COUNTERS_OFFSET_BASE (1UL << 62)
    #else
        #define UVM_EVENTS_OFFSET_BASE   (1UL << 31)
        #define UVM_COUNTERS_OFFSET_BASE (1UL << 30)
    #endif
#endif // defined(__linux___)

//
// UvmAddSession
//
#define UVM_ADD_SESSION                                               UVM_IOCTL_BASE(10)

typedef struct
{
    unsigned            pidTarget;           // IN
#ifdef __linux__
    NvP64               countersBaseAddress NV_ALIGN_BYTES(8); // IN
    int                 sessionIndex;        // OUT (session index that got added)
#endif
    NV_STATUS          rmStatus;           // OUT
} UVM_ADD_SESSION_PARAMS;

//
// UvmRemoveSession
//
#define UVM_REMOVE_SESSION                                             UVM_IOCTL_BASE(11)

typedef struct
{
#ifdef __linux__
    int                 sessionIndex;   // IN (session index to be removed)
#endif
    NV_STATUS          rmStatus;      // OUT
} UVM_REMOVE_SESSION_PARAMS;


#define UVM_MAX_COUNTERS_PER_IOCTL_CALL 32

//
// UvmEnableCounters
//
#define UVM_ENABLE_COUNTERS                                           UVM_IOCTL_BASE(12)

typedef struct
{
#ifdef __linux__
    int                 sessionIndex;                               // IN
#endif
    UvmCounterConfig    config[UVM_MAX_COUNTERS_PER_IOCTL_CALL];    // IN
    unsigned            count;                                      // IN
    NV_STATUS          rmStatus;                                  // OUT
} UVM_ENABLE_COUNTERS_PARAMS;

//
// UvmMapCounter
//
#define UVM_MAP_COUNTER                                               UVM_IOCTL_BASE(13)

typedef struct
{
#ifdef __linux__
    int                 sessionIndex;   // IN
#endif
    UvmCounterScope     scope;          // IN
    UvmCounterName      counterName;    // IN
    UvmGpuUuid          gpuUuid;        // IN
    NvP64               addr    NV_ALIGN_BYTES(8); // OUT
    NV_STATUS          rmStatus;      // OUT
} UVM_MAP_COUNTER_PARAMS;

//
// UvmCreateEventQueue
//
#define UVM_CREATE_EVENT_QUEUE                                        UVM_IOCTL_BASE(14)

typedef struct
{
#ifdef __linux__
    int                     sessionIndex;       // IN
#endif
    unsigned                eventQueueIndex;    // OUT
    NvU64                   queueSize;          // IN
    NvU64                   notificationCount;  // IN
#if defined(WIN32) || defined(WIN64)
    NvU64                   notificationHandle; // IN
#endif
    UvmEventTimeStampType   timeStampType;      // IN
    NV_STATUS               rmStatus;           // OUT
} UVM_CREATE_EVENT_QUEUE_PARAMS;

//
// UvmRemoveEventQueue
//
#define UVM_REMOVE_EVENT_QUEUE                                        UVM_IOCTL_BASE(15)

typedef struct
{
#ifdef __linux__
    int         sessionIndex;       // IN
#endif
    unsigned    eventQueueIndex;    // IN
    NV_STATUS   rmStatus;           // OUT
} UVM_REMOVE_EVENT_QUEUE_PARAMS;

//
// UvmMapEventQueue
//
#define UVM_MAP_EVENT_QUEUE                                           UVM_IOCTL_BASE(16)

typedef struct
{
#ifdef __linux__
    int         sessionIndex;       // IN
#endif
    unsigned    eventQueueIndex;    // IN
    NvP64       userRODataAddr;     // IN
    NvP64       userRWDataAddr;     // IN
    NvP64       readIndexAddr;      // OUT
    NvP64       writeIndexAddr;     // OUT
    NvP64       queueBufferAddr;    // OUT
    NV_STATUS   rmStatus;           // OUT
} UVM_MAP_EVENT_QUEUE_PARAMS;

//
// UvmEnableEvent
//
#define UVM_EVENT_CTRL                                                UVM_IOCTL_BASE(17)

typedef struct
{
#ifdef __linux__
    int          sessionIndex;      // IN
#endif
    unsigned     eventQueueIndex;   // IN
    int          eventType;         // IN
    unsigned     enable;            // IN
    NV_STATUS    rmStatus;          // OUT
} UVM_EVENT_CTRL_PARAMS;

//
// UvmRegisterMpsServer
//
#define UVM_REGISTER_MPS_SERVER                                       UVM_IOCTL_BASE(18)

typedef struct
{
    UvmGpuUuid          gpuUuidArray[UVM_MAX_GPUS];  // IN
    unsigned            numGpus;        // IN
    NvU64               serverId;       // OUT
    NV_STATUS           rmStatus;       // OUT
} UVM_REGISTER_MPS_SERVER_PARAMS;

//
// UvmRegisterMpsClient
//
#define UVM_REGISTER_MPS_CLIENT                                       UVM_IOCTL_BASE(19)

typedef struct
{
    NvU64               serverId;       // IN
    NV_STATUS           rmStatus;       // OUT
} UVM_REGISTER_MPS_CLIENT_PARAMS;

//
// UvmEventGetGpuUuidTable
//
#define UVM_GET_GPU_UUID_TABLE                                        UVM_IOCTL_BASE(20)

typedef struct
{
    UvmGpuUuid          gpuUuidArray[UVM_MAX_GPUS];  // OUT
    unsigned            validCount;                  // OUT
    NV_STATUS           rmStatus;                    // OUT
} UVM_GET_GPU_UUID_TABLE_PARAMS;

#if defined(WIN32) || defined(WIN64)
//
// UvmRegionSetBacking
//
#define UVM_REGION_SET_BACKING                                        UVM_IOCTL_BASE(21)

typedef struct
{
    UvmGpuUuid         gpuUuid;
    NvU32              hAllocation; // IN
    NvP64              vaAddr; // IN
    NvU64              regionLength; // IN
    NV_STATUS          rmStatus; // OUT
} UVM_REGION_SET_BACKING_PARAMS;

//
// UvmRegionUnsetBacking
//
#define UVM_REGION_UNSET_BACKING                                      UVM_IOCTL_BASE(22)

typedef struct
{
    NvP64              vaAddr; // IN
    NvU64              regionLength; // IN
    NV_STATUS          rmStatus; // OUT
} UVM_REGION_UNSET_BACKING_PARAMS;

#endif

#define UVM_CREATE_RANGE_GROUP                                        UVM_IOCTL_BASE(23)

typedef struct
{
    UvmRangeGroupId    rangeGroupId; // OUT
    NV_STATUS          rmStatus; // OUT
} UVM_CREATE_RANGE_GROUP_PARAMS;

#define UVM_DESTROY_RANGE_GROUP                                       UVM_IOCTL_BASE(24)

typedef struct
{
    UvmRangeGroupId    rangeGroupId; // IN
    NV_STATUS          rmStatus; // OUT
} UVM_DESTROY_RANGE_GROUP_PARAMS;

//
// UvmRegisterGpuVaSpace
//
#define UVM_REGISTER_GPU_VASPACE                                      UVM_IOCTL_BASE(25)

typedef struct
{
    UvmGpuUuid         gpuUuid; // IN
    NvHandle           hClient; // IN
    NvHandle           hVaSpace; // IN
    NV_STATUS          rmStatus; // OUT
} UVM_REGISTER_GPU_VASPACE_PARAMS;

//
// UvmUnregisterGpuVaSpace
//
#define UVM_UNREGISTER_GPU_VASPACE                                    UVM_IOCTL_BASE(26)

typedef struct
{
    UvmGpuUuid         gpuUuid; // IN
    NV_STATUS          rmStatus; // OUT
} UVM_UNREGISTER_GPU_VASPACE_PARAMS;

//
// UvmRegisterChannel
//
#define UVM_REGISTER_CHANNEL                                          UVM_IOCTL_BASE(27)

typedef struct
{
    UvmGpuUuid         gpuUuid;                         // IN
    NvHandle           hClientFromRm;                   // IN
    NvHandle           hChannelFromRm;                  // IN
    unsigned long long base;                            // IN
    unsigned long long length;                          // IN
    NV_STATUS          rmStatus;                        // OUT
} UVM_REGISTER_CHANNEL_PARAMS;

//
// UvmRegisterChannel
//
#define UVM_UNREGISTER_CHANNEL                                        UVM_IOCTL_BASE(28)

typedef struct
{
    UvmGpuUuid         gpuUuid;                         // IN
    NvHandle           hChannelFromRm;                  // IN
    NV_STATUS          rmStatus;                        // OUT
} UVM_UNREGISTER_CHANNEL_PARAMS;


//
// UvmSetRangeGroup
//
#define UVM_SET_RANGE_GROUP                                           UVM_IOCTL_BASE(29)

typedef struct
{
    UvmRangeGroupId    rangeGroupId; // IN
    unsigned long long requestedBase; // IN
    unsigned long long length; // IN
    NV_STATUS          rmStatus; // OUT
} UVM_SET_RANGE_GROUP_PARAMS;

//
// UvmAlloc
//
#define UVM_ALLOC                                                     UVM_IOCTL_BASE(30)
typedef struct
{
    UvmRangeGroupId     rangeGroupId;                    // IN
    unsigned long long  base;                            // IN
    unsigned long long  length;                          // IN
    UvmProcessorUuid    homeProcessorUuid;               // IN
    UvmGpuAttributes    perGpuAttributes[UVM_MAX_GPUS];  // IN
    unsigned long long  gpuAttributesCount;              // IN
    NV_STATUS           rmStatus;                        // OUT
} UVM_ALLOC_PARAMS;

//
// UvmMapRmAllocation
//
#define UVM_MAP_RM_ALLOCATION                                         UVM_IOCTL_BASE(31)
typedef struct
{
    unsigned long long  base;                            // IN
    unsigned long long  length;                          // IN
    UvmGpuAttributes    perGpuAttributes[UVM_MAX_GPUS];  // IN
    unsigned long long  gpuAttributesCount;              // IN
    NvU32               hClientFromRm;                   // IN
    NvU32               hMemoryFromRm;                   // IN
    NV_STATUS           rmStatus;                        // OUT
} UVM_MAP_RM_ALLOCATION_PARAMS;

//
// UvmFree
//
#define UVM_FREE                                                      UVM_IOCTL_BASE(32)
typedef struct
{
    unsigned long long  base;                            // IN
    unsigned long long  length;                          // IN
    NV_STATUS           rmStatus;                        // OUT
} UVM_FREE_PARAMS;

//
// UvmMemMap
//
#define UVM_MEM_MAP                                                   UVM_IOCTL_BASE(33)

typedef struct
{
    NvP64              regionBase; // IN
    NvU64              regionLength; // IN
    NV_STATUS          rmStatus; // OUT
} UVM_MEM_MAP_PARAMS;

//
// Temporary ioctls which should be removed before UVM 8 release
// Number backwards from 2047 - highest custom ioctl function number 
// windows can handle.
//

//
// UvmIs8Supported
//
#define UVM_IS_8_SUPPORTED                                            UVM_IOCTL_BASE(2047)

typedef struct
{
    NvU32              is8Supported; // OUT
    NV_STATUS          rmStatus; // OUT
} UVM_IS_8_SUPPORTED_PARAMS;


#ifdef __cplusplus
}
#endif

#endif // _UVM_IOCTL_H
